Traffic light signaling and operation binary
Circuit 54 produces an output signal in line 56 which indicates that the error check is complete and there is no error in the received data. The signal in line 56 initiates the address check by circuit 57 which compares the address of the received data pulses with the stored address of the controller in matrix 58 and produces a signal in line 59 when the addresses are the same. This signal is fed to control logic circuit Immediately following this, the logic control circuit 28 produce an initiating signal in line 60 which controls gates in the shift register 52 that feed the lamp data stored in the shift register to buffer register Suitable delays are included to insure that the buffer register is cleared before the data from shift register 52 is inserted into it.
At the next zero crossing of the 60 cycle line voltage, a signal in line 62 feeds the contents of register 61 via gates 63 to the lamp buffer register 64 which is located in the lamp drive system At this point, the. The lamps are energized by the output of the buffer register 64 which feeds by parallel lines 65 to lamp relays 66 which in turn each control lamp triacs 67 that power the individual lamps Thus, the lamps switch on or off at a zero crossing of the 60 cycle line voltage.
Switching at this point avoids power line current surges which would occur at switching at high excursion points of the line voltage. Power line current surges can produce faults in the system. The format of a data signal train is illustrated in FIG. The address bits are at the end of the train. The end bit detector 69 detects the first bit in the train when it reaches the end 52a of the shift register.
When this bit reaches the end of the shift register, it triggers the end bit pulse shown by the waveforms in FIG. The end bit pulse occurs during the pause interval denoted P between the trains.
Immediately following the end bit pulse, the cyclic check compare circuit 54 and address compare circuit 57 function to produce pulses in lines 56 and 59 denoted the valid message and address pulses which indicates that a full and complete message without error has been received in the shift register and it is addressed to the local controller.
The control logic circuit 28 responds to these pulses pulsing line 60 to in effect strobe the buffer register. In other words, the data in the shift register 52 is gated into the buffer register Immediately after this, vehicle and pedestrian data from logic circuits 71 and 72 triggered by detectors 73 and 74, respectively, is gated into the data stage of the shift register in parallel fashion.
This occurs during the interval denoted load shift register in FIG. It will be noted that all the action from the detection of the end bit in the shift register 52 to the point where the shift register is loaded with vehicle and pedestrian data, occurs during the pause interval denoted P between the data signal trains. At the end of this pause interval, the register is ready to shift out the vehicle and pedestrian data in serial fashion feeding it to the transmitter For this purpose, line 73 feeds the vehicle and pedestrian data to transmitter 24 for transmission to the master controller receiver.
In transmitter 24, vehicle and pedestrian data in serial form is fed via electronic switch 74 to line driver The output of line driver 75 is coupled via transformer 76 to the two conductor transmission lines If the controller is local controller A, then transmission line 77 is the same as line 4 shown in FIGS.
If the controller is controller B, then the transmission line 77 connects the equivalent of transmitter 24 in controller B to receiver 25 in controller A. The receiver 25 in controller A receives signals from the equivalent of transmitter 24 in controller B via transmission line These signals are coupled by transformer 79 to threshold detector 81 and fed from the detector via electronic switch 74 to line driver 75 for transmission to the master controller.
This is the case when the switch 74 is conditioned as illustrated in FIG. Failure detector circuit 82 detects failures in the output of threshold detector 81 and line driver 75 and deenergizes bypass relay 84 when a failure occurs.
Relay 84 operates switch 85 in line 77 which shortcircuits signals directly from transmission line 78 to transmission line 77 bypassing the detector and line driver. This shortcircuit system is substantially the same as the one de scribed above with reference to receiver 20 and transmitter The data signal train as already mentioned is a bipolar waveform which carries both data as binary information and synchronous timing.
Clearly, the message train format is binary digital. The binary information is carried in the transitions of the waveform from plus to minus. These are the bipolar transitions. The waveform always makes a transition at clock time and these transitions generate a delayed window which brackets the expected time for the clock transition.
A binary 1 is transmitted if the waveform transition during the window goes in the same direction as the previous transition at the previous clock transition. A binary is transmitted if the waveform transition goes opposite to the previous clock transition. This technique using a window provides an improvement in signal to noise ratio by restricting the time that receiving circuits are allowed to be sensitive to line noise.
Also, the waveform must exceed a positive or negative threshold before any transitions are allowed and so a further signal to noise ratio improvement is effected. These thresholds can be set to further noise rejection as desired. The composition of the data signal train from the master starts with a line pause in the two conductor transmission line 9.
This is followed by a negative line transition in the waveform called the start pulse as shown in the waveforms A of FIGS. The waveforms in FIG.
The other waveforms in these figures illustrate the signals at various points in the communication process logic circuit shown in FIG. The waveforms in the figures are lettered as are the points in the decoder logic circuit identifying where the waveforms occur.
As shown in FIG. This is rectified by rectifier 93 producing waveform G which triggers one shot delay circuit 94 producing waveform C. These are gated by NAND gate 95 which triggers one shot multi-vibrator 96 producing the waveform H which is the clock pulses.
The output of differentiator 92 which is waveform B is clipped by clipper circuit 97 producing waveform D that is fed along the waveform H to a D flip-flop circuit One stage output denoted Q1 of flip flop 98 is gated with waveform D by Exclusive OR gate 99 producing a pulse train F.
The clock pulses H strobe this pulse train into the shift register This pulse train is the message of the format shown in FIG. The length of the data signal train transmitted by the master controller and therefore the length of the message, can be arbitrarily long and is only limited by the size of the shift register and buffer registers at the local controller.
The message includes data for controlling the lamps. This data transmission scheme with the data and clock carried by the bipolar waveform shown in FIGS. In addition, only a single pair of lines the two conductor transmission lines are needed to service a multitude of local intersections. A detailed block diagram of the backup system in each local controller is illustrated in FIG.
The backup system is controlled by a multitude of lines in a cable 11 from the master controller. The lines on the cable are energized by the backup transmitter 10 at the master controller.
Signals are transmitted over these lines continually even while normal operation is proceeding and so at each local controller, the backup system is ever ready to take over and control the lamps at the intersection should the normal system fail. Also a signal from the master controller represented by a bit in register 52 can initiate the backup system by producing a signal in line to logic circuits A signal from control logic system 28 in line to the backup system initiates insertion of the backup system commands over lines into the lamp buffer register This is shown in FIG.
Within the backup system 30, as illustrated in FIG. The cycle select lines are fed to cycle select circuit and the offset lines are fed to offset select circuit The outputs of these selectors are fed to the backup system matrices circuits which are preprogrammed for the particular intersection.
The lines in cable 11 are all energized with volt ac which is either on or off and so the signalling over these lines is binary. Depending upon the signal combinations in these lines, a particular cycle length, cycle intervals, interval end times, and cycle offset are selected from the matrices.
These are selected as binary numbers which are inserted from the matrices into other circuits as described below. The binary number representing cycle length is inserted from the matrices into the one percent timer circuit via lines The interval between these overflow pulses is related to the cycle length number inserted from the matrices.
It is convenient if such overflow pulses occur during the interval of the commanded cycle. Then, each overflow pulse represents a 1 percent interval of the commanded cycle. The overflow pulses, denoted 1 percent timer pulses, are fed to the percent counter which continues to count until the output compares with the offset command output from the matrices.
The offset command output is inserted from the matrices via lines into offset compare circuit When the offset command number in comparator is the same as the count number in counter , a stop pulse is produced and fed to the 1 percent timer which stops timing and so the pulse flow from timer to counter stops. If the local intersection is at the proper offset, then at the time of the stop pulse from the compare circuit , the appropriate offset select line in cable from the master controller will open briefly causing the offset matrices in to output a signal in lines which causes the stop signal output from comparator to be removed and the 1 percent timer will continue pulsing the counter which will continue to count in 1 percent increments of the cycle.
Thus, the counter counts to during the interval of each cycle length called for by the master controller. This count is offset in time as dictated by the offset signal from the master controller. The functioning of the circuit is as follows: On the other hand, if the counter is not at the right number when the offset select line opens, counter will keep on counting, but will stop as soon as it reaches 20 and then wait for the next timing signal from the master controller.
The count numbers from the counter are compared with the interval end time numbers triggered by the matrices via line from interval end time matrix The interval end time matrix produces a set of interval numbers which are each associated with a portion of the cycle. Each time one of these interval numbers from matrix compares with the count number from counter , comparator triggers the interval counter which in effect counts the number of intervals in sequence during a cycle.
These count numbers from counter are decoded by interval decoder which selects the set of lamps at the intersection which are to be energized during the inverval from interval selector This energizes the interval definition matrix which feeds a parallel set of signals to the lamp buffer register 63 via gates as shown in FIG. In this manner, the backup system takes over when signalled over line by logic controller 28 to gates and controls the lamps at the intersection when a failure occurs in the normal operating system or when selected by the master controller as dictated by the control logic circuit The received data is a train of pulse levels representing binary l and binary 0.
These are received into a shift register, the data stages of which are each identified with a specific light at the intersection and so, depending upon whether the signal is binary 1 or binary 0, that light is turned on or off. The two element transmission line carries the data signal train from the master controller to a first local controller which receives the signal train and simultaneously transmits it to a second local controller and meanwhile stores the received signal train in a shift register.
The second local controller receives the signal train transmitted from the first local controller and also stores it in a shift register and transmits it to a third local controller and so forth. Thus, the signal train transmitted by the master controller is stored in each of the local controllers. Then, in the local controllers each local controller compares the received signal address with the local address while making a cyclic check for errors in the received signal train.
If the received signal train checks alright, the local controller 7 to which it is addressed feeds the data bits from the shift register to a buffer register that controls the lights at the intersection turning lights off or on as dictated by the data bits. At the next transmission interval, the signal train is addressed to another local controller and is received by all of the local controllers replacing the previously received signal train stored in the shift registers in all of the local controllers.
This sequence of transmission by the master controller continues until the buffer registers in all of the local controllers are loaded with controlling signals for the light at the intersections and then the transmission sequence is repeated. The local controllers are also equipped to store signals initiated by vehicles and pedestrians at or near the intersection.
Switches initiated by vehicles and pedestrians are monitored and data gathered at each intersection. These data are inserted into the shift register at the local controller between the intervals of transmission from the master controller and after the received signal train stored in the shift register has been examined for address and has shifted into the buffer register at the local controller to which the signal train is addressed.
The vehicle and pedestrian detection signals are then shifted out of the shift register and to a transmitter at the local controller. The local controllers transmit these signals representing vehicle and pedestrian data in relay fashion back to the master controller just as the master controller signal trains are transmitted relay fashion from local controller to local controller. Thus, at each local controller, the shift register which receives the signal train from the master controller each time a signal train is transmitted by the master controller also serves to briefly store in parallel fashion numbers representing vehicle and pedestrian density and feed these numbers out in serial fashion to a transmitter which transmits them back toward the master controller.
The vehicle and pedestrian data need not be preceded by an address signal indicative of the intersection from whence they come since the local controller transmits immediately after its message has been received from the master controller. Therefore, the master controller knows which local controller is transmitting. At the master controller these signals serve as inputs to alter the control programs for the intersection.
Other objects and features of the present invention will be apparent in view of the following specific description of an embodiment of the invention taken in conjunction with the figures in which:.
Vehicle traffic control in its simplest form involves repetitively cycling the lights through a series of fixed time intervals. During each interval, a fixed set of lights is turned on. The sum of all interval durations in the cycle equals the cycle length. Several specific phases can be recognized during a typical cycle. A phase is a part of a cycle allocated to a movement of traffic.
The cycle split as defined herein refers to the way time in a cycle is assigned to all the phases. For example, at a simple crossing of a street running north and south with a street running east and west, the split may be if the traffic loads on the two streets are equal or they may be if the traffic loads are not equal.
At a three way intersection of two major arteries with a secondary street, the split may be 4 O and so forth. The intersection is further complicated when vehicle and pedestrian detectors are included. It is sometimes desired that the signals from vehicle detectors dictate the intervals and even determine whether additional intervals will be added to the cycle.
Where vehicle detectors are used, the exact signal cycle at an intersection may be determined on a cycle by cycle basis by the vehicle detectors on at least some of the vehicle approaches and in some cases on all vehicle approaches.
Where, some of the approaches are equipped with vehicle detectors, this control is called semi-traffic actuated and where all approaches are equipped, it is called full traffic actuated control. Traffic flow in a city can usually be improved by providing synchronization of the signals at a set of intersections.
The intersection offset is the number of seconds or the percent of cycle length after a reference time that a particular interval should start. A sophisticated computerized traffic control system for controlling the multitude of complex intersections in a typical city ideally is capable of unlimited variation of cycle length, cycle intervals, and phases, cycle split, and cycle offset.
It includes vehicle and pedestrian detectors wherever such controls are significant and so there should be a continual flow of signals from the master control to the local controllers and from local controllers to the master controller.
In addition, all programs at the master controller should be easily modified by traffic engineer inputs from a teletype terminal and other equipment which is keyed from police, fire, and emergency alarm systems in the city. The local controllers and the transmission system between the local controllers and master controller and the format of signals in conjunction with modern computer equipments available for use at the master controller provide a system which approaches this ideal.
At the master controller, a control computer 1 which may be a general purpose computer controls programs for all lights at all intersections in terms of the cycles, phases, and intervals, and the split and offset. This information is stored and subject to continual inputs from the intersections, the traffic engineer teletype, and other inputs from police, fire, and emergency monitors in the city.
These factors are all fed to the control computer to determine the on-off sequences for each light at each intersection including the pedestrian as well as vehicle lights. All of the inputs are represented by the digital storage 2 which feeds fixed programs to the computer and the digital input 3 which feeds variable data to the computer except the vehicle and pedestrian data from the intersections.
Vehicle and pedestrian data from the intersections is fed to the computer via the two conductor transmission line 4 from the first local controller in the chain; this is local controller A.
The data from the local controllers is received by data receiver 5 and stored in buffer register 6. This data is fed from the buffer register to the control computer to select signals to the local controllers depending upon predetermined programs and conditions measured at the intersection.
The normal operation output from the control computer consisting of the signals which make up the data signal trains is fed from the control computer to transmit buffer register 7 as parallel signals. From the buffer register 7, the signals are shifted out at clock rate defining the data signal trains and they are converted into a bipolar form of signal with binary information carried in transitions of the waveform and such that a transition is made at each clock pulse.
This waveform is described herein with respect to FIGS. The data signal train is transmitted by the data transmitter 8 over transmission line 9 which is a two wire line. The line 9 goes to a receiver in the first local controller which is local controller A.
Backup signal transmitter 10 at the master controller continually transmits backup signals to all of the local controllers over a common transmission line This transmission line 11 consists of a multitude of wires carrying l 10 volt ac which turns on and off to signal over each wire.
At each local controller, a backup system shown in FIGS. The backup signals are not used to control the lights unless the local controller logic has issued a command to switch to backup. The matrix at each backup system in each local controller is programmed in view of the particular needs of the intersection and so local controllers for intersections having substantially different needs will respond differently to the signals transmitted over transmission lines 11 from the backup transmitter.
A display 12 is provided at the master controller displays to the traffic engineer and staff, traffic situations, and other information which may warrant a variation of the programs in the control computer. For example, the display may be a map of the city showing all arteries and intersections with lights and other variable information on the display to reveal the operation of the lights at the intersections.
Two local controllers are shown A and B, each containing identical electronic equipments and so they operate identically except for the different matrix programs in their backup systems. At each local controller such as local controller A is a receiver 20 and transmitter 21 which receive and relay the data signal trains from the master controller transmitter 8 on to the next controller which in this case is local controller B.
The binary pulse train containing address, data, special bits, and check bits is fed into a shift register in registers 22 which also contain circuits for performing a cyclic check of the received pulses to determine errors and an address check to ascertain whether or not the signal train is intended for local controller A.
Between transmissions of data signal trains from the master controller and immediately after a signal train is received by local controller A which is addressed to that controller, pedestrian, vehicle, and intersection status data at intersection A are fed via the buffers and registers 22 to the transmitter 24 which immediately transmits these numbers serial fashion along with the address of controller A over the transmission line 4 to the receiver in the master controller.
The other local controllers will perform in the same manner to transmit such data back to the master controller. In each case the local controller will transmit this data representing pedestrian, vehicle, and intersection status during the transmission interval immediately following receiving a data signal train addressed to the local controller. Thus, the address of the local controller need not be transmitted with the data as the master controller will know from whence comes the data and is programmed accordingly.
The pedestrian, vehicle, and intersection status data is relayed from local controller to local controller until it arrives at the master controller. For this purpose, the transmitter 24 and receiver 25 in each local controller receive transmitted data from another local controller and pass it on to still another. In local controller A, the receiver 25 receives data from local controller B and this is conducted uninterrupted over line 26 to transmitter 24 and retransmitted onto the master controller receiver 5.
A switch in the transmitter 24 controlled by line 27 from logic controller 28 switches the transmitter between line 29 from the registers carrying pedestrian, vehicle, and intersection status data from local controller A, to line 26 which carries the same sort of data from another local controller.
Thus, transmitter 24 transmits this data from the local controllers during the same intervals that the master controller transmits data signal trains. The pedestrian, vehicle, and intersection status data from a given local controller can be transmitted during any interval, even the same interval that a data signal train is transmitted to that same local controller. All data flowing into a controller whether addressed to the controller or not, and all data generated at the controller goes through the same shift register.
The data is shifted into the register during one interval and them shifted out during the following interval while newly arrived data is shifted in. The pedestrian, vehicle, and intersection status data from a given controller is conveniently transmitted from the controller during the interval following receipt by the controller of data from the master which is addressed to that controller.
In that case, the status data need not contain the controller address. A backup system 30 in each local controller is energized by lines from cable 11 from the backup transmitter at the master controller. All lines in the cable 11 run to all backup systems in all local controllers and so all signals in these lines are simultaneously fed to all the backup systems in all the local controllers. However, each backup system in each local controller, as already mentioned, contains a program selection matrix which is a preprogrammed diode matrix.
The signals in the cable 11 select the preprograms in the backup systems. The backup systems in the local controllers run continuously even while normal operation is without error or fault. When an error or fault occurs in a local controller, the backup system in that controller takes over as dictated by logic control 28 and the backup system feeds through line 31 parallel sets of signals for controlling the lamps at the intersections.
These are fed through the registers 22 to the lamp drive circuits 23 using the same circuits which feed signals during normal operations controlling the lamps. The rate of transmission of the data signal trains from the master controller to the local controllers is about twice per second.
The format of data signal trains transmitted is shown by the waveform type diagrams in FIG. A complete cycle of transmission includes the sequential transmission of data signal trains to all of the local controllers which are designated A, B, C-N. The data signal trains are conveniently transmitted in the sequence A, B, CN, the complete set of trains being transmitted in 0. The intervals between signal trains are denoted p. The format denoted Master Transmits initiates all transmission and reception between local controllers and this includes the transmission from the local controllers backto the master controller of the pedestrian, vehicle, and status data.
The waveform denoted Master Receive indicates which intersection pedestrian and vehicle data is received at the master controller during the transmission intervals. Clearly, in the interval following transmission of a data signal train to controller A, the pedestrian and vehicle data from controller A is received by the master controller and so forth. The waveforms denoted A Receives and A Repeats are the same for all local controllers and are the same format as the transmissions from the master controller.
The next waveform denoted A Accepts Data represents the brief interval that pedestrian, vehicle, and status data generated at intersection A is inserted into the buffer in registers 22 at controller A. The logic data applied to the input side thereof is transferred to its output side upon the positive going transition or leading edge of the clock signal.
The flip-flop circuits produce logic levels which are fed into a sequence memory circuit through a memory decoder 75a and also to eight program memory circuits, only four of which are shown, namely: The transmission to the respective program memory circuits are through their associated memory decoders 80aa.
It is to be observed that the program memory circuits are connected in parallel to the output of the flip-flop circuits as is the sequence memory circuit Therefore, the output of the flip-flop circuits are transmitted simultaneously to the sequence memory circuit 75 and all of the program memory circuits, such as The sequence memory circuit 75 is programmed to function as a counter.
However, the program may be varied so that the count may be in a numerical sequence as in the Wilkes principle. The output of the sequence memory circuit 75 provides the address of the next word in the sequence.
In addition thereto, the sixth bit of the output of the sequence memory circuit 75 provides a clock input to a program select circuit More specifically, the clock input transfers the logic levels on the input of D-type flip-flop circuits 90 and 91 in the manner previously described for the flip-flop circuits This action inhibits a change in program until the end of a cycle.
The input signals for the flip-flop circuits 90 and 91 may be from any suitable source such as a time clock. The program selecting apparatus will preset or precondition the flip-flop circuits 90 and 91 for a prescribed program operation.
At the end of each cycle, which is when the last word of the sequence memory circuit 75 is being addressed, the sequence memory circuit 75 emits an output signal to change the state of the flip-flop circuits 90 and Connected to the output of the flip-flop circuits 90 and 91 is a conventional 4 to 16 decoder circuit The output of the decoder 95 includes, in the exemplary embodiment, eight output terminals.
The program memory circuits, such as program memory circuits are connected respectively to the output terminals of the decoder 95 and the program memory circuits are respectively enabled or disabled by the signals appearing on the associated output terminal on the decoder circuit Thus, for each given program selection only one of the program memory circuits will be operated through the program selector circuit More specifically, for each different program selection a different program memory circuit will be operated.
Only one program memory circuit is operated during a given selected program. The decoder 95 is conventional and is procuced by Signetics Corp. The flip-flops 90 and 91 with the decoder 95 serve to inhibit the changing of a program in the middle of a cycle and would tend to reduce operation changes from false signals. The program memory circuits, such as program memory circuits , receive simultaneously the outorder to activate the associated traffic displays or lights. The output terminals of the program memory circuits are connected in the OR configuration to an output buffer Hence, the only data that is presented to the output buffer 99 is the word being addressed in the enabled memory circuit of the memory circuits The output buffer 99 may be any suitable signal conditioning device which changes the output signals to render the same compatible with the signal transmission facilities.
In the exemplary embodiment, the output signals from the buffer 99 are transmitted in parallel over the conductors When a serial converter is employed for series transmission the number of conductors may be reduced. From the foregoing, it is to be observed that the output of the sequence memory decoder 75a is gated through the flip-flop circuits The output of the flip-flop circuits is transmitted to the input of the sequence memory decoder a and to the input sides of the program memory circuits The logic levels produced by selected program memory circuit are transmitted to the output buffer 99, which then transmits the code pulses over the conductors to the local controllers At the end of each cycle, the sequence memory circuit 75 operates the flip-flop circuits and 91 of the program select circuit A presettable binary counter circuit has clock pulses applied to its pulse terminal 6 which controls the logic on its output terminals 12, 2 and 9.
The counter circuit is an integrated circuit manufactured by Texas Instruments as SN 74, Connected to the output of the counter circuit is a decoder circuit which includes NOR gate circuits , NAND gate circuits The gates of the decoder circuit will selectively have an output 1 potential or a zero potential.
When the output potential ofa given gate is O or low, its associated lamp is illuminated. When the output potential of a given gate is l or high, its associated lamp is extinguished. For example, if the output at pins 12, 2 and 9 of the counter circuit were all low , then the output potentials for the gate circuits are low, and the associated red lamps will be illuminated. Also, the output potential of the gate circuit is high, or at a 1 potential, and the red lamp connected to its output is extinguished.
At this time, the output of the gates , , and will be high to extinguish the yellow lamps associated therewith. The gate circuit will be low to illuminate the green lamp associated therewith. The traffic lights are well-known and are conventionally operated in a well-known manner through the associated gate circuits The traffic lights or displays with the operating circuits thereof are designated red, yellow and green for the respective phases A-D. With the output of the NAND gate at zero potential, the input terminal of the counter circuit is at low potential and the input terminal of counter circuits are high.
Therefore, the counters are reset to zero and held in that condition. The counters are conventional counters of the type manufactured by Signetics or Texas Instruments as SN With the input terminal thereof at zero potential the counter is enabled for counting.
The frequency divider , which has a frequency of one pulse per second, is connected to a. II flip-flop circuit The clock pulse output from the JK flip-flop is transmitted simultaneously to the counters and over a conductor Each time the counter receives a clock pulse from the. IK flip-flop circuit , which is once every 2 seconds, the output thereof is advanced by one binary digit.
The counters are not enabled at this time to count. Connected to the output circuits of the binary counters and are switching networks, and and connected to the other side of the switching networks and are NAND gate circuits and It is apparent to one skilled in the art that pull up resistors at the input of the NAND gates may be required.